1. Field of the Invention
This invention relates generally to a method and apparatus for connecting a semiconductor chip to external electrical conductor leads and, more particularly, to a universal substrate having a fixed input/output assignment and adapted to receive at least two different but allied semiconductor chips having unique wire-out requirements.
2. Discussion of the Related Art
Semiconductor devices typically comprise one or more semiconductor chips designed for performing a desired function. The manufacture of semiconductor devices begins with the manufacture of the semiconductor chips. Semiconductor chips are first produced in a wafer form. The semiconductor chips are subsequently diced from the wafer into individual chips and then packaged. Individual chips, or multiple chips, may be packaged on a suitable substrate such as a multilayer ceramic (MLC) substrate or package, for instance.
Multilayer ceramic substrates are known in the art and thus only briefly described herein. In addition, a substrate may also be referred to as a package, wherein the terms are used interchangeably herein below. MLC substrates typically comprise a number of layers of ceramic material, including metallizations, internal wiring networks, vias, and bond pads. Each layer is first formed of an unfired ceramic material, then punched and patterned according to a desired semiconductor chip package design. The layers are then assembled and aligned together in a predetermined order. The unfired ceramic material is then fired and flattened, as necessary. The MLC thus produced is used for making chip-to-package interconnection to a semiconductor chip for which it was designed. Upon a positioning and attaching of the semiconductor chip onto the MLC substrate, the chip can then be electrically connected thereto, as appropriate. Alternatively, the MLC may include a cavity for receiving the semiconductor chip therein. Electrical interconnection between the MLC package and the semiconductor chip can be made using wirebonding, flip-chip, thermally activated bonding, and/or other chip-to-package interconnect techniques known in the art. Wirebonding, for instance, involves the use of wires for connecting a wirebond pad on the semiconductor chip with a corresponding wirebond pad on the MLC. The substrate also includes input/output pins, or other suitable form of input/output connections, for interfacing the chip to a next level of packaging, for example, to a printed circuit board, or the like.
In addition, for MLC substrates containing a cavity, it is typical for a solid ground or solid power plane to be screened onto a cavity layer, i.e., a layer having a cavity therein. Screening of a solid ground or power plane upon a cavity layer presents a number of manufacturing problems in the high volume manufacturing of substrates, as known by those skilled in the art. Still further, conventional MLC substrates typically contain a layer which includes wirebond pads, vias, and redistribution lines, all on the same layer, further requiring multiple patterning steps.
Referring now to FIG. 1, a semiconductor chip 10 is generally characterized by a series of bond pads 12 positioned about an outer perimeter thereof. The bond pads facilitate the making of chip-to-package interconnections, that is, for making electrical connections between the chip and a substrate package. The semiconductor chip 10 can further be characterized as having a particular wire-out requirement. The wire-out requirement of the semiconductor chip is that particular connection requirement for connecting each of the particular wirebond pads of the semiconductor chip to a wirebond pad of the packaging substrate. The wirebond pads, vias, and wiring networks of the packaging substrate are designed in conjunction with the wire-out requirement of the semiconductor chip and further in accordance with a particular I/O pin assignment of the substrate package. In addition, the particular I/O pin assignment of the substrate is driven by the requirements of the next level of packaging, e.g., the printed circuit board.
Wire-out requirements for a particular semiconductor chip are subject to change, for instance, as follows. During a manufacturing run of a particular semiconductor chip design, semiconductor chips may be produced which do not all possess the same level of functionality, even though they were manufactured according to the same processing steps. A sort of the produced chips by their functional capability may lead to a sorting of the chips into several groups, wherein each group possesses different wire-out requirements. For instance, let's assume that a semiconductor chip design is for a 200 MHZ microprocessor. A particular run of the manufacturing process for the 200 MHZ processor, however, may produce processor chips which fall into one of several groups. That is, out of a single manufacturing run, one-third of the chips might be sorted and categorized into a 200 MHZ group, one-third of the chips into a 160 MHZ group, and the remaining one-third of the chips into a 150 MHZ group. The groups of processor chips thus lead to different wire-out requirements for each group. As a result, while the chips may have the same number of wirebond pads, each group of chips has a distinct wire-out. In other instances, changes may be deliberately made to the manufacturing process, for the purpose of making small modifications to the semiconductor chips such that the chips can function in different applications, such as providing additional features, etc. In this later instance, the revisions of a particular chip generally result in the revised chip design having a unique wire-out, also.
Furthermore, it is known in the art for the packaging industry to utilize multiple bond pads on a semiconductor chip for wirebond attachment to the same wirebond pad on the substrate. In that case, the particular wirebond pad of the substrate was often widened to accommodate these multiple wirebonds. This has usually been done for the purpose of tying a signal pad on the chip to a voltage wirebond pad on the substrate. If the latter was attempted with a signal wirebond pad, the avoidance of crossing any of the wirebond leads would force the constraint that the die pads on the chip must be adjacent, or in extremely close proximity.
When a semiconductor chip is designed and/or modified as discussed herein above, it is quite common to find that there is no package available which is compatible with the chip for the purpose of interfacing the chip to the next level of packaging. Accordingly, a unique package compatible with the chip is required. Furthermore, as a result, there are literally thousands of single-purpose semiconductor chip packages available.
Fabricating specialized packages for each new chip design or modification becomes expensive, particularly for chip designs having 200-300 pads, each requiring connection to the package for signal, power, or ground. Unless a chip is properly designed for a pre-existing package, connections by way of wirebonds or thermally activated bonding connections cannot be made. If the chip has not been laid out so that direct connections from the edges of a chip can be made to corresponding signal, power, or ground pads on an available chip package, a special package must then be designed and fabricated. The later results in significant additional costs per chip package.
In addition, in a high volume manufacturing environment, a substrate manufacturer may employ a particular class of substrate packages for packaging chips from several customers. However, each of the customers typically has different requirements which drive unique substrate designs for each chip. Furthermore, a single customer may have multiple allied chip designs or versions (i.e., 486DX2, 486DX4, etc.) which also results in multiple substrate designs for that particular customer.
In the highly volatile commodities market of the present day semiconductor device industry, customer requirements and volumes frequently change in very short periods of time. As a result, the substrate manufacturer must adapt and shift production rapidly from one part number to another while minimizing unusable part numbers in inventory. Manufactured substrates which have been designed for a particular chip are rendered obsolete once the chip requirements change. Additionally, the packaging market is highly cost competitive. A small price increase greater than the competition can result in a loss of orders for a manufacturer.
It would thus be desirable to provide a single universal substrate design for use in packaging at least two semiconductor chips having different wire-out requirements.